Continuous miniaturization of the contact areas on semiconductor wafers gives rise to problems, in particular, in the context of the functional test at the wafer level of a semiconductor chip since, with an increasing number of contact areas per test in conjunction with miniaturization of the dimensioning of the contact areas, increased contact problems occur during the test. Problems also arise when bonding contact areas which have already been damaged by the functional test on account of the test tips, with the result that increased rejects occur during production.
Document U.S. Pat. No. 5,506,499 discloses providing a test area which is separate from the contact area for bonding and is electrically connected to the contact area. This configuration requires additional chip area in order to accommodate the additional test area besides each contact area on the semiconductor chip. The solution disclosed in U.S. Pat. No. 5,506,499 leads to an enlargement of the required chip area and is at odds with miniaturization endeavors in semiconductor technology.